Infrasonicon icon. Click here for home page.INFRASONICON: Time-Compressing Infrasonic Recordings to Discover New Sounds, by Clark Huckaby


Data Converter: Technical Description

Choosing Data Converter Design. The Data Converter linearly transforms either frequency-modulated (FM) or voltage-analog infrasonic signals into a pulse-code-modulated (PCM) digital stream. A block diagram and general description is included in Part 2 of the Overview. At infrasonic frequencies, a wide range of designs could match or surpass my version's maximum performance (12-bit resolution and 268-Hz sampling). For example, a fast microprocessor could directly measure time between the FM signal's state transitions and sequentially report averages during precise sampling periods. Or a slower processor working with external timing hardware could do the job. I chose to put the onus on analog hardware and kept the digital side minimal. This is more a reflection of my analog background than a design necessity.

Data Converter Construction Technique. The Data Converter is a mixed-mode system. It must minimize cross-talk between three distinct signal types: frequency-analog (FM), voltage-analog, and digital. I used ground-plane-enhanced point-to-point wiring on a single 6 X 8-inch pre-punched perfboard. Each functional block has a separate ground plane. Figure 1 is a photo of the assembly and Figures 2, 3 and 4 show the schematics. Figure and component numbers are internal references within this page only.

Figure 1: Labeled photos of Data Converter assembly.
Figure 1. Photos of Data Converter assembly, with functional blocks and some other parts labeled. Clear plastic dust cover (made from two CD "jewel case" lids) is removed. Top: top view of board. Bottom: front panel view. Front and rear panels (or brackets) are made from 3/4-inch right-angle aluminum stock.

I planned each functional block's component layout for minimum point-to-point interconnection distance beneath the board. Using templates cut from 0.1-inch-grid graph paper, I maximized local ground plane areas while allowing non-grounded component pins free access to holes. Next, I cut 5-mil-thick brass foil to match the templates, sanded the bottom surface, and applied that side to the top of the perfboard using heat-resistant epoxy cement. During assembly I splayed out grounded component pins and soldered them to the top of the brass ground planes.

The assembly's 5-V supply terminals are bypassed with a 150-F electrolytic capacitor (C1 in Figure 2, bottom; diode D1 protects the chips if supply polarity is reversed, by shorting out the power supply to blow its output fuse). The power distribution architecture is quite obvious in the photo (Figure 1). Fanning out from C1, separate ground and +5 VDC wires (green and yellow insulation, respectively, in Figure 1) serve individual functional blocks; this is a strict "star" distribution scheme, except the digital block and lock-fail detector ground planes are daisy-chained. Where the yellow +5V supply wires connect to chips, tantalum capacitors on short leads bypass chip VDD pins to adjacent ground planes. The ADC chip (U5) is at the edge of the analog block's ground plane nearest the digital block (the microcontroller; see below). Of course, one could make a PCB instead of using this "enhanced point-to-point" technique; such a design would also need separate ground planes and properly bypassed DC distribution. This keeps cross-talk and noise below the system's digital resolution limit.

Demodulator Block. A schematic diagram of the demodulator is shown in the upper portion of Figure 2. It uses U1, a CD4046B phase-locked loop (PLL) CMOS IC (datasheet: http://focus.ti.com/lit/ds/symlink/cd4046b.pdf). I included voltage divider R1/R2 because certain inputs have 6-V swings. R1 is bypassed with a jumper for 5-V inputs. R2 also prevents floating the signal input when J1 is disconnected. In this condition (no input signal), the voltage-controlled oscillator (VCO) free-running frequency is set by C2 and R3/R4. Trim-pot R4 allows adjustment between about 600 and 1500 Hz. Normally it is tuned to match f0, the expected FM carrier frequency. I'll assume f0 equals the nominal 1 KHz in this circuit description.

Figure 2: Schematic diagram of deomdulator and lock-fail detector blocks, and power distribution for whole Data Converter assembly.
Figure 2. Schematic diagram of demodulator and lock-fail detector. Also included (at bottom) is a representation of DC power supply and ground distribution for entire Data Converter assembly. At bottom right is a key to ground abbreviations used in the schematics on this page. Component numbers continue sequentially in Figure 3 and Figure 4 of this page.

In free-running mode, U1's VCO output (pin 4) and phase comparator (X-OR gate) output (pin 2) each have a symmetrical duty cycle and 5-V swing. Loop filter R5/C3 integrates this signal into a triangle waveform offset by +2.5 V, and applies it to the VCO input (pin 9). Coupling a 1-KHz signal to J1 leads to phase lock, in which the comparator output frequency doubles (2 KHz), but its duty cycle (50 %) and thus the VCO control voltage (+2.5 V) are unchanged. This is because the VCO output lags a 1-KHz input by exactly 90 degrees. Note that the input duty cycle must be 50 % (symmetrical).

When modulation causes the input to depart from f0 = 1 KHz, the VCO phase lag angle tracks this change. The X-OR gate converts phase lag angle to duty cycle, the loop filter converts duty cycle to VCO control voltage, and the VCO converts control voltage to frequency. The feedback loop is closed through the X-OR gate. The result is demodulation--the VCO control voltage changes precisely in direct proportion to input frequency (non-linearity is about one percent). I took the raw voltage-analog infrasonic signal from U1's buffered output at pin 10. In this case, "raw" means it contains ripple whose fundamental frequency equals 2f0 (more about this below).

When Phase Lock Fails: Lock Fail Detector Block. An ideal PLL would remain locked at input frequencies between DC (0 Hz) and 2f0 (2000 Hz). The real lock range of the circuit in Figure 2 is about 200 to 1800 Hz. But the capture range, the band the input must transit before phase lock can occur, is narrower. Loop filter design requires trading dynamic performance off against output ripple amplitude. In my compromise, the capture range is 745 to 1285 Hz, and the output ripple is 120 mVPP. The maximum frequency tracking speed (slew rate) is 200 Hz/millisecond; this limits the signal bandwidth in an amplitude-dependent manner: At maximum amplitude, phase lock fails at signal frequencies greater than 37 Hz, but this increases by one octave for each 6-dB decrease in amplitude.

When the FM input exceeds the PLL's lock range (headroom) or slew rate (amplitude-dependent bandwidth), phase lock--and thus demodulation--fails. Severe distortion results. In Figure 2, dual flip-flop U2 serves as a lock failure detector, a "watch-dog" for PLL function. The locked PLL's VCO output (U1, pin 4) always lags its input (pin 14) by more than zero and less than 180 degrees. In this case, U2A holds LED D2 ("Failure Event" indicator) off. Lock failure disrupts the orderly alternation of U2A's inputs causing D2 to emit light pulses. At infrasonic frequencies, re-capturing phase lock always requires enough time for the pulse trains to be visible. But in case the operator is not looking, U2B is clocked by the event, holding LED D3 ("Failure History" indicator) on until reset button SW1 is pressed.

Signal Conditioning: Voltage-Analog Block. I'll henceforth just call this section the "analog block" for short, recognizing that FM is also analog. As shown in Figure 3 (at top of diagram), a header socket mated with a shorting plug serves as the analog block's input-select switch, choosing between the demodulator's raw infrasonic signal or a signal taken directly form an infrasonic transducer having a voltage output, via RCA jack J3. Clamp diodes D6 and D7 help protect the the block's input stage if peak signal voltages are < 0V or > +5V.

The analog block performs two vital functions: (1) low-pass (LP) filtering and (2) amplitude scaling to match the 0 to +5 V input range of the analog-to-digital converter (ADC). Its DC-coupled variable filter and gain/offset stages use OPA2340 CMOS rail-to-rail dual op-amps U3 and U4 (datasheet: http://focus.ti.com/lit/ds/symlink/opa4340.pdf). Voltage follower U3A drives first-order LP filter R11/C6. Inverting amplifier U4A hosts variable gain (0 to 21 dB) and DC-offset trim-pots R14 and R16. Finally, U4B acts as a second-order LP filter that adds 4 dB gain in the pass-band. Op-amp U3B is not used (note in the schematic that this is not the best way to tie off a spare op-amp; generally it's better to ground only the "+" input and hook the "-" input to the ouput).


Figure 3: Schematic diagram of voltage analog block.
Figure 3. Schematic diagram of voltage-analog block of the Data Converter assembly.

The analog block's overall LP filter characteristic is third-order, attenuating signals by 18 dB per octave as frequency increases beyond a critical (the corner or cutoff) frequency, fC. As Figure 3's inset shows, there is a choice of three cutoff frequencies: 20, 50, and 160 Hz. Shorting plugs mated with female headers complete the parallel capacitor networks denoted by C6, C7, and C8 in the schematic. For the flattest pass-band and sharpest cutoff, the same shorting plug position should be used in each of the three networks. I referred heavily to Don Lancaster's cookbook (Don Lancaster [1995] "Active Filter Cookbook" [2nd Edition, 17th Printing] Synergetics Press, Thatcher, AZ; ISBN 1-882193-31-8) for this design.

Ideally, LP filtration makes unwanted signals smaller than the 12-bit ADC's resolution limit (-72 dBFS [dB referred to full scale]). There are two possible unwanted signals: (1) the demodulator output's carrier harmonic ripple (120 mVPP at 2 KHz), and (2) any signal component exceeding one-half the sampling frequency (called the Nyquist frequency; for a thorough treatise on digital audio, see Ken C. Pohlmann [2005] "Principles of Digital Audio" [5th Edition] McGraw-Hill; ISBN 0-07-144156-5 [Note the depiction of water surface ripples, a famous analogy for sound, on the cover art.]).

The worst-case condition for the 2-KHz demodulator ripple is when analog block gain is maximum (25 dB). Ripple would be amplified to 2.1 Vpp if left unfiltered. This is 7.5 dB below full scale (5 Vpp), so 64.5 dB (72 minus 7.5) attenuation is needed at 2 KHz. The least-aggressive filter setting (160 Hz) just reaches this mark, so all gain/filter combinations are safe, ripple-wise. Regarding the second type of unwanted signal, an ADC converts signals greater than the Nyquist frequency into aliases. These spurious products are related to the original frequency by their difference to the sampling frequency. Flat, alias-free response right up to the Nyquist frequency requires advanced high-order filter design. To minimize aliasing, I usually recorded with the highest possible sampling frequency (268 Hz), and used the 20- or 50-Hz third-order LP filter setting. Detectable aliases are present in certain recordings, though; a clear example is illustrated and discussed in Analysis of Flywheel Recording Reveals Aliasing.

ADC and the Digital Block (Microcontroller BS2). As shown in Figure 4, the 12-bit sampling analog-to-digital converter (ADC) is a Linear Technology LTC1286 chip (U5; datasheet begins on page 9 of the Parallax AppKit at http://www.parallax.com/dl/docs/prod/appkit/ltc1298.pdf). Physically it is located at the edge of the analog block's ground plane (see Figure 1) and receives its ground reference there. The processed infrasonic signal feeds its inverting analog input (pin 3). This compensates for signal inversion at op-amp U4A in the analog block (Figure 3). Overall, increasing frequency at the Data Converter's FM input, or increasing voltage at the assembly's voltage input, increases quantization values at the digital output.

Figure 4: ADC and Digital Block, the latter using a Parallax BS2 module.
Figure 4. Schematic diagram of ADC chip and the digital block. The latter uses a Parallax Basic Stamp-2 (BS2-IC) microcontroller module.

A Parallax BS2-IC module (U6) interrogates the ADC via a three-wire synchronous serial data link. Previously, via a PC hooked to J2, the BS2 was loaded with program SampLoop.bs2 (see Download Table, below; you can open and read it in a text editor like NotePad; it is comment-rich, containing descriptive information beyond what's given here). This source code is written in PBasic (Parallax-Basic) of course; the following description contains PBasic jargon (in UPPER CASE). The program waits for start button SW3 to close, then turns LED D5 on and SEROUTs a null byte (%00000000) to the PC; its purpose is described below. Finally, the program enters a loop that alternately obtains a sample value from the ADC and then passes it to the PC. This loop continues until reset button SW2 is pressed.

The BS2 handles 12-bit quantization values (ranging 0 to 4095) as 16-bit words. BIT0 (most significant bit or MSB) through BIT11 (least significant or LSB) contain the data, and BIT12 through BIT15 are always zeros. A SEROUT command sends each word to the PC as two bytes in the order BYTE0, BYTE1.

I initially tried setting the sampling frequency by slaving the BS2 to an external clock. But lack of synchronization to the stamp's own clock caused jitter (unequal time between samples). Instead, the simplest and best approach was to let the BS2's on-board oscillator serve as master clock. Streamlined for minimum execution time, the program loop cycles reliably at 268 Hz. The sampling frequency can be predictably reduced by inserting a PAUSE command, which makes it 1000/(3.97 + PAUSE value) Hz. Note that including a null PAUSE line (PAUSE 0) lowers the sampling frequency to 252 Hz; thus the presence of a PAUSE line itself adds about 0.24 milliseconds to loop excecution, regardless of its value. In other words, PAUSE N accurately adds N + 0.24 milliseconds to the period between samples.

Software Download
ProgramCompressed (Zipped) VersionUn-compressed File*
Sampling Program for BS2SampLoop.zipSampLoop.bs2
Recording Program for PCRECINFRA.zipRECINFRA.BAS
Metering Program for PCINFRAMTR.zipINFRAMTR.BAS
*My browser opens these un-compressed files as if they were HTML, so the lines wrap together into a continuous block of text. If this happens on yours, try right-clicking on the text and select "view source" to see the properly layed-out code.

Making WAV Files: Metering and Recording Software. Coded in QBASIC, my recording and metering programs are RECINFRA.BAS and INFRAMTR.BAS, respectively (see Download Table, above; you can open and read them in a text editor like NotePad; they are comment-rich, containing more complete descriptions than I am giving here). I wrote them for my old-fashioned 166-MHz Pentium-S PC hosting Windows 95 and sporting a DB-25 serial com port.

Microsoft designed the popular WAV format for either 8- or 16-bit digital audio. I used 16-bit files and acknowledge that my 12-bit data uses 25% more disc space than it deserves in theory. Since a 16-bit WAV file's samples are signed (2's complement) integers ranging from -32,768 to 32,767, my programs multiply each 12-bit value by 16 and then subtract the constant 32,760. This normalization uses only integer math and is therefore lossless.

With each 12-bit sample arriving as two serial bytes (see above), the PC must process them in the correct frame. Randomly tapping a continuous data stream would record nonsense half the time. My minimalist solution: before beginning to take samples, SampLoop.bs2 instructs the Basic Stamp to SEROUT a null "start byte" that prompts the PC software to enter a loop for processing the asynchronous serial data which follow. I've recorded WAV files containing 2,894,400 samples (3 hours at 268 Hz) with glitch-free performance.

Recording program RECINFRA.BAS starts each new file with a 44-character WAV file header that contains the format descriptors and file parameters (see http://ccrma.stanford.edu/courses/422/projects/WaveFormat/). Pre-set parameters include number of channels (one), audio format (PCM), and bits per sample (16). The user enters file size (number of samples) and playback sampling frequency. The latter determines the time compression factor. For example, if sampling frequencies are 268 Hz for recording and 44,100 Hz for playback, 165-fold time compression results.

My "real-time" metering program (INFRAMTR.BAS) plots sample values on the screen's horizontal axis while scrolling time vertically. It has 65-pixel amplitude resolution with adjustable sensitivity. It can update with each sample or average any number of consecutive samples, as entered by the user. Scrolling the display with each update, it also lists the numerical sample values or averages. Compared to audio recording, "setting a level" takes extra time and patience at infrasonic frequencies. In the case of my Data Converter, which is DC-coupled, it also involves adjusting the DC offset trim-pot (whose setting interacts with the gain trim-pot).
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See Part 2 of the Overview for a more general discussion of the Infrasonicon's Data Converter, including a block diagram. Also see the technical description of the Interface Unit, which scales FM signals to match the Data Converter's nominal carrier frequency. The following are links to technical descriptions of various transducers: Optical Probe, Water Theremin, and Audio Amplitude Detector.


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